View ISL8023AIRTAJZ_4701430.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 3a/4a low quiescent current high efficiency synchronous buck regulator isl8023, isl8024 the isl8023, isl8024 is a hi gh efficiency, monolithic, synchronous step-down dc/dc converter that can deliver up to 3a/4a continuous output current from a 2.7v to 5.5v input supply. it uses current control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the isl8023, isl8024 integrates a pair of low on-resistance p-channel and n-channel inte rnal mosfets to maximize efficiency and minimize external component count. the 100% duty-cycle operation allows less than 200mv dropout voltage at 4a output current. the operational frequency, pulse-width modulation (pwm), is adjustable from 500khz to 4mhz. connecting fs pin high sets th e default frequency to 1mhz switching frequency allows the use of small external components. the isl8023, isl8024 can be configured for discontinuous or forced continuous operation at light load. forced continuous operation reduces noise and rf interference while discontinuous mode provides high efficiency by reducing switching losses at light loads. fault protection is provided by internal hiccup mode current limiting during short circuit and overcurrent conditions, an output over voltage comparator and over-temperature monitor circuit. a power good output voltage monitor indicates when the output is in regulation. the isl8023, isl8024 offers a 1ms power-good (pg) timer at power-up. when in shutdown, isl8023, isl8024 discharges the output capacitor. other features include internal fixed or adjustable soft-start, internal/external compensation, and thermal shutdown. the isl8023, isl8024 is offered in a space saving in a 16 ld 3x3 qfn lead free package with exposed pad lead frames for low thermal with 1mm maximum height. the complete converter occupies less than 0.22 in 2 area. various fixed output voltage are available upon request. see ordering information for more detail. features ? high efficiency synchronous buck regulator with up to 95% efficiency ? 0.8% reference accuracy over-temperature/load/line ? start-up with pre-biased output ? internal soft-start - 1ms or adjustable ? soft-stop output disc harge during disabled ? adjustable frequency from 500khz to 4mhz - default at 1mhz (8023/24), 2mhz (8023a/24a) ? external synchronization up to 4mhz ? negative oc protection ? dc/dc pol modules ?c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ?portable instruments ? test and measurement systems ? li-ion battery powered devices applications ? dc/dc pol modules ? c/up, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ?portable instruments ? test and measurement systems ? li-ion battery powered devices related literature see an1660 , ?3a/4a low quiescent current high efficiency synchronous buck regulator? 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) figure 1. efficiency t = +25c v in = 5v efficiency (%) 3.3v out pwm 3.3v out pfm caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. december 22, 2011 fn7812.0
isl8023, isl8024 2 fn7812.0 december 22, 2011 pin configuration isl8023, isl8024 (16 ld tqfn) top view 1 3 4 vin vdd sync vin phase phase comp 2 7 5 6 fb pgnd en fs pg ss 8 11 9 10 16 13 15 14 12 sgnd pgnd phase pin descriptions pin number symbol description 1, 16 vin input supply voltage. connect two 22f ceramic capacitors to power ground. 2 vdd input supply voltage for the logic. connect vin pin. 3 pg power good is an open-drain output. use 10k to 100k pull-up resistor connecting between vin and pg. at power-up or en hi , pg rising edge is delayed by 1ms up on output reached within regulation. 4 sync mode selection pin. connect to logic high or input voltage vin for pwm mode. connect to logic low or ground for pfm mode. connect to an external function generator for synchronization with the positive edge trigger. there is an internal 1mw pull down resistor to prevent an undefined logic state in case of synin pin float. 5 en regulator enable pin. enable the output when driven to high. shut down the chip and discharge output capacitor when driven to low. there is an internal 1mw pull down resistor to prevent an undefined logic state in case of en pin float. 6 fs this pin sets the oscillator switching frequency, using a resistor, rfs, from the fs pin to gnd. the frequency of operation may be programmed between 500khz to 4mhz. the default frequency is 1mhz and configured for internal compensation if fs is connected to vin. 7 ss ss is used to adjust the soft start time. set to sg nd for internal 1ms rise time. connect a capacitor from ss to sgnd to adjust the soft start time. do not use more than 33nf per ic. 8, 9 comp, fb the feedback network of the regulator, vfb, is the negative input to the transconductance error amplifier. comp is the output of the amplifier if fs resistor is used. otherwise comp is disconnected thru a mosfet for internal compensation. must co nnect comp to sgnd in internal compensation mode. the output voltage is set by an external re sistor divider connected to vfb. with a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6v reference. there is an internal compensation to meet a typical application. additional external network across comp and sgnd might be required to improve the loop compensation of the amplifier operation. in addition, the regulator power-good and under-vo ltage protection circuitry use vfb to monitor the regulator output voltage 10 sgnd signal ground. 11, 12 pgnd power ground. 13, 14, 15 phase switching node connection. connect to one terminal of the inductor. exposed pad the exposed pad must be connected to the sg nd pin for proper electrical performance. place as much vias as possible under the pad connecting to sgnd plane for optimal thermal performance.
isl8023, isl8024 3 fn7812.0 december 22, 2011 typical application block diagram ordering information part number (notes 1, 2) part marking output voltage (v) temp. range (c) package (pb-free) pkg. dwg. # isl8023irtajz 023a adjustable -40 to +85 16 ld 3x3 tqfn l16.3x3d isl8024irtajz 024a adjustable -40 to +85 16 ld 3x3 tqfn l16.3x3d ISL8023AIRTAJZ 23aa adjustable -40 to +85 16 ld 3x3 tqfn l16.3x3d isl8024airtajz 24aa adjustable -40 to +85 16 ld 3x3 tqfn l16.3x3d notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl8023, isl8024 . for more information on msl please see techbrief tb363 . l 1h phase pgnd vfb vin en pg ss input 2.7v to 5.5v output 1.8v/4a c1 22f isl8023, isl8024 c2 r2 200k r3 100k 2 x 22f sgnd c3* 4.7pf r1 100k figure 2. typical application diagram comp sync fs vin * c3 is optional. recommend to put a placeholder for it. check loop analysis first before use. vdd sgnd table 1. component selection table v out 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v 3.6 c1 22f 22f 22f 22f 22f 22f 22f c2 4x22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f 2 x 22f c3 4.7pf 4.7pf 4.7pf 4.7pf 4.7pf 4.7pf 4.7pf l1 0.47~1h 0.47~1h 0.47~1h 0.68~1.5h 0.68~1.5h 1~2.2h 1~2.2h r2 33k 100k 150k 200k 316k 450k 500k r3 100k 100k 100k 100k 100k 100k 100k
isl8023, isl8024 4 fn7812.0 december 22, 2011 figure 3. functional block diagram phase + + csa + + ocp skip + + + slope comp slope soft start soft eamp comp pwm/pfm logic controller protection hs driver vfb + 0.85*vref pg sync shutdown vin pgnd oscillator zero-cross sensing bandgap scp + 0.5v en shutdown 1ms delay 55pf 100k sgnd 3pf 6k - - - - - - - vdd comp 100 shutdown ls driver fs iset threshold vref + neg current sensing p n + 0.6v - uv ov ss
isl8023, isl8024 5 fn7812.0 december 22, 2011 absolute maximum ratings (reference to gnd) thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v en, fs, pg, sync, vfb . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3v (100ns)/(dc) to 6.5v (dc) comp, ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 4a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance ja (c/w) jc (c/w) 16 ld tqfn package (notes 4, 5) . . . . . 45 6.5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameter limits ar e established over the recommended operating conditions and the typical specification ar e measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en = v in , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c parameter symbol test conditions min (note 6) typ max (note 6) units input supply v in undervoltage lockout threshold v uvlo rising, no load 2.5 2.7 v falling, no load 2.2 2.4 v quiescent supply current i vin sync = gnd, no load at the output 50 a sync = gnd, no load at the output and no switches switching 50 60 a sync = vin, f s = 1mhz, no load at the output 8 15 ma shut down supply current i sd sync = gnd, v in = 5.5v, en = low 5 7 a output regulation reference voltage - isl8023irz, isl8024irz v ref 0.595 0.600 0.605 v vfb bias current - isl8023irz, isl8024irz i vfb vfb = 0.75v 0.1 a line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) 0.2 %/v soft-start ramp time cycle ss = sgnd 1 ms soft-start charging current i ss v ss = 0.1v 1.2 1.6 2.0 a overcurrent protection current limit blanking time t ocon 17 clock pulses overcurrent and auto restart period t ocoff 8 ss cycle positive peak current limit i plimit 4a application 5.2 6.5 7.8 a 3a application 3.9 4.8 5.9 a peak skip limit i skip 4a application (test at 3.6v) 0.9 1.2 1.5 a 3a application (test at 3.6v) 0.65 0.9 1.15 a zero cross threshold -200 200 ma negative current limit i nlimit -3.0 -2.4 -1.8 a
isl8023, isl8024 6 fn7812.0 december 22, 2011 compensation error amplifier trans-conductance fs = vin 80 a/v fs with resistor 150 a/v trans-resistance rt 0.15 0.2 0.25 phase p-channel mosfet on-resistance v in = 5v, i o = 200ma 35 45 55 m v in = 2.7v, i o = 200ma 50 70 90 m n-channel mosfet on-resistance v in = 5v, i o = 200ma 12 19 25 m v in = 2.7v, i o = 200ma 20 28 37 m phase maximum duty cycle 100 % phase minimum on-time sync = high 140 ns oscillator nominal switching frequency fsw fs = vin 800 1000 1200 khz fs with rs = 402k 490 khz fs with rs = 42.2k 4200 khz sync logic low to high transition range 0.70 0.75 0.80 v sync hysteresis 0.15 v sync logic input leakage current v in = 3.6v 3.6 5 a pg output low voltage 0.3 v delay time (rising edge) 0.5 1 2 ms pg pin leakage current 0.01 0.1 a ovp pg rising threshold 0.80 v uvp pg rising threshold 80 85 90 % uvp pg hysteresis 5% pgood delay time (falling edge) 15 s en logic input low 0.4 v logic input high 0.9 v en logic input leakage current 0.1 1 a thermal shutdown 150 c thermal shutdown hysteresis 25 c note: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design electrical specifications unless otherwise noted, all parameter limits ar e established over the recommended operating conditions and the typical specification ar e measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en = v in , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl8023, isl8024 7 fn7812.0 december 22, 2011 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 4a). figure 4. efficiency vs load (1mhz 3.3 v in pwm) figure 5. efficiency vs load (1mhz 3.3 v in pfm) figure 6. efficiency vs load ( 1mhz 5v in pwm) figure 7. efficiency vs load ( 1mhz 5v in pfm ) figure 8. power dissipation vs load (1mhz, v out = 1.8v) figure 9. v out regulation vs load (1mhz, v out = 1.2v) 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) efficiency (%) 1.2v out 1.5v out 1.8v out 2.5v out 3.3v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.2v out 1.5v out 1.8v out 2.5v out 3.3v out i out (a) efficiency (%) 0 0.18 0.36 0.54 0.72 0.90 1.08 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) power dissipation (w) 3.3v in pwm mode 5v in pwm mode 1.208 1.214 1.220 1.226 1.232 1.238 1.244 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) v out (v) 3.3v in pwm mode 5v in pfm mode 3.3v in pfm mode 5v in pwm mode
isl8023, isl8024 8 fn7812.0 december 22, 2011 figure 10. v out regulation vs load (1mhz, v out = 1.5v) figure 11. v out regulation vs load (1mhz, v out = 1.8v) figure 12. v out regulation vs load (1mhz, v out = 2.5v) figure 13. v out regulation vs load (1mhz, v out = 3.3v) figure 14. output voltage regulation vs v in (pwm v out =1.8) figure 15. output voltage regulation vs v in (pfm v out =1.8v) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 4a). (continued) 1.499 1.504 1.509 1.514 1.519 1.524 1.529 0.00.51.01.52.02.53.03.54.0 i out (a) v out (v) 3.3v in pfm mode 5v in pwm mode 3.3v in pwm mode 5v in pfm mode 1.794 1.800 1.806 1.812 1.818 1.824 1.830 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) v out (v) 3.3v in pfm mode 5v in pwm mode 3.3v in pwm mode 5v in pfm mode 2.492 2.500 2.508 2.516 2.524 2.532 2.540 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i out (a) v out (v) 3.3v in pfm mode 5v in pwm mode 3.3v in pwm mode 5v in pfm mode 3.300 3.309 3.318 3.327 3.336 3.345 3.354 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5v in pfm mode 5v in pwm mode i out (a) v out (v) 1.785 1.790 1.795 1.800 1.805 1.810 1.815 2.02.53.03.54.04.55.05.56.0 4a load 0a load 2a load v in (v) v out (v) 1.788 1.796 1.804 1.812 1.820 1.828 1.836 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v in (v) v out (v) 4a load 0a load 2a load
isl8023, isl8024 9 fn7812.0 december 22, 2011 figure 16. steady state operation at no load (pwm) figure 17. steady state operation at no load (pfm) figure 18. steady state operation with full load figure 19. load transient (pwm) figure 20. load transient (pfm) figure 21. soft-start with no load (pwm) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 4a). (continued) phase 2v/div v out ripple 20mv/div i l 1a/div phase 2v/div v out ripple 20mv/div i l 1a/div phase 2v/div v out ripple 20mv/div i l 2a/div v out ripple 50mv/div i l 2a/div v out ripple 50mv/div i l 2a/div en 2v/div v out 1v/div i l 1a/div pg 5v/div
isl8023, isl8024 10 fn7812.0 december 22, 2011 figure 22. soft-start at no load (pfm) figure 23. soft-start with pre-biased 1v figure 24. soft-start at full load figure 25. soft-discharge shutdown figure 26. steady state operation at no load with frequency = 2mhz figure 27. steady state operation at full load with frequency = 2mhz typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 4a). (continued) en 2v/div v out 1v/div i l 1a/div pg 2v/div en 2v/div v out 1v/div i l 1a/div pg 5v/div en 2v/div v out 1v/div i l 2a/div pg 5v/div en 2v/div v out 1v/div i l 1a/div pg 5v/div phase 5v/div v out ripple 20mv/div i l 0.5a/div sync 5v/div phase 5v/div v out ripple 20mv/div i l 2a/div sync 5v/div
isl8023, isl8024 11 fn7812.0 december 22, 2011 figure 28. steady state operation at no load with frequency = 4mhz figure 29. steady state operation at full load (pwm) with frequency = 4mhz figure 30. output short circuit figure 31. output short circuit recovery typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 4a). (continued) phase 5v/div v out ripple 20mv/div i l 0.2a/div sync 5v/div phase 5v/div v out ripple 20mv/div i l 1a/div sync 5v/div phase 5v/div v out 1v/div i l 2a/div sync 5v/div phase 5v/div v out 1v/div i l 2a/div sync 5v/div typical operating performance for a part unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 4a). figure 32. steady state operation at no load (pwm) figure 33. steady state operation at no load (pfm) phase 2v/div v out ripple 20mv/div i l 0.5a/div phase 2v/div v out ripple 20mv/div i l 1a/div
isl8023, isl8024 12 fn7812.0 december 22, 2011 figure 34. steady state operation with full load figure 35. soft-start with no load (pwm) figure 36. soft-start at no load (pfm) figure 37. soft-start at full load figure 38. soft-discharge shutdown typical operating performance for a part unless otherwise noted, operating conditions are: t a = +25c, v vin = 5v, en = v in , sync = v in , l = 1.0h, c 1 = 22f, c 2 = 2 x 22f, i out = 0a to 4a). (continued) phase 2v/div v out ripple 20mv/div i l 2a/div i l 1a/div en 2v/div pg 5v/div v out 1v/div v out 1v/div i l 1a/div en 2v/div pg 5v/div en 2v/div v out 1v/div i l 1a/div pg 5v/div en 2v/div v out 1v/div i l 1a/div pg 5v/div
isl8023, isl8024 13 fn7812.0 december 22, 2011 theory of operation the isl8023, isl8024 is a step-down switching regulator optimized for battery-powered handheld applications. the regulator operates at 1mhz fixed default switching frequency, when fs is connected to vin, under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (pcb) area. by connecting a resistor fr om fs to sgnd, the operational frequency adjustable range is 500k hz to 4mhz. at light load, the regulator reduces the switching freq uency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the quiescent current when the output is not loaded is typically only 45a. the supply curr ent is typically only 5a when the regulator is shut down. pwm control scheme pulling the sync pin hi (>0.8v) forces the converter into pwm mode, regardless of output current. the isl8023, isl8024 employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse- by-pulse current limiting. figure 3 on page 4 shows the functional block diagram. the current loop consists of the oscillator, the pwm comparator, current sensing circuit and the slope compensation for the current loop stability. the slope compensation is 440mv/ts, which changed wi th frequency. the gain for the current sensing ci rcuit is typically 200mv/a. the control reference for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier cs a and the slope compensation reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-fet and turn on the n-channel mosfet. the n-fet stays on until the end of the pwm cycle. figure 39 shows the typical operating waveforms during the pwm operatio n. the dotted lines illustrate the sum of the slope compensati on ramp and the current-sense amplifier?s csa output. the output voltage is regulated by controlling the v eamp voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that co nverts the voltage error signal to a current output. the voltage loop is internally compensated with the 55pf and 100k rc network. the maximum eamp voltage output is precisely clamped to 1.6v. skip mode pulling the sync pin lo (<0.4v) forces the converter into pfm mode. the isl8023, isl8024 ente rs a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 40 illustrates the skip-mode operation. a zero-cross sensing circuit shown in figure 4 on page 7monitors the n-fet current for zero crossing. when 8 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. during the eight detecting cycles, the current in th e inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in figure 4 on page 7. each pulse cycle is still synchronized by the pwm clock. the p-fet is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak skip current limit value. then the inductor current is discharging to 0a and stays at zero. the internal clock is disabled. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-fet will be turned on again at the rising ed ge of the internal clock as it repeats the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. figure 39. pwm operation waveforms v eamp v csa duty cycle i l v out
isl8023, isl8024 14 fn7812.0 december 22, 2011 frequency adjust the frequency of operation is fixed at 1mhz and internal compensation when fs is tied to vin. adjustable frequency range from 500khz to 4mhz via simple resistor connecting fs to sgnd according to equation 1: overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in figure 4. the current sensing circuit has a gain of 200mv/a, from the p-fet current to the csa output. when the csa output reaches the threshold, the ocp comparator is trippled to turn off the p-fet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. upon de tection of the initial overcurrent condition, the overcurrent fault counter is set to 1. if, on the subsequent cycle, another overcu rrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the regulato r will be shut down under an overcurrent fault condition. an overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of eighth soft-start periods. at the end of the eight soft-start wait period, the fault counters are reset and soft-start is attempted again. if the overcurrent condition goes away during the delay of four soft-start periods, the output will resume back into regulation point after hiccup mode expires. negative current protection similar to the overcurrent, the negative current protection is realized by monitoring the current across the low-side n-fet, as shown in figure 4 on page 7. when the valley point of the inductor current reached -3a for 4 consecutive cycles, both p-fet and n-fet are off. the 100 in parallel to the n-fet will activate discharging the output into regulation. the control will begin to switch when output is within regulation. the regulator will be in pfm for 20s before switching to pwm if necessary. pg pg is an open-drain output of a window comparator that continuously monitors the buck re gulator output voltage. pg is actively held low when en is low and during the buck regulator soft-start period. after 1ms dela y of the soft-start period, pg becomes high impedance as long as the output voltage is within nominal regulation voltage set by vfb. when vfb drops 15% below or raises 0.6v above the nominal regulation voltage, the isl8023, isl8024 pulls pg low. any fault condition forces pg low until the fault condition is cleared by attempts to soft-start. for logic level output voltages, connect an external pull-up resistor, r 1 , between pg and vin. a 100k resistor works well in most applications. uvlo when the input voltage is below th e undervoltage lock-out (uvlo) threshold, the regulator is disabled. figure 40. skip mode operation waveforms clock i l v out nominal +1.5% nominal pfm current limit 0 8 cycles pwm pfm nominal -1.5% pwm load current r t k [] 220 10 3 ? f osc khz [] ------------------------------ 14 ? = (eq. 1)
isl8023, isl8024 15 fn7812.0 december 22, 2011 soft start-up the soft-start-up reduces the in-r ush current during the start-up. the soft-start block outputs a ramp reference to the input of the error amplifier. this voltage ramp limits the inductor current as well as the output voltage speed so that the output voltage rises in a controlled fashion. when vfb is less than 0.1v at the beginning of the soft-start, the switching frequency is reduced to 200khz so that the output can start-up smoothly at light load condition. during soft-start, the ic operates in the skip mode to support pre-biased output condition. tie ss to sgnd for internal soft start approximately 1ms. connect a capacitor from ss to sgnd to adjust the soft start time. this capacitor, along with an internal 1.6a current source sets the soft-start interval of the converter, t ss as shown by equation 2. c ss must be less than 33nf to insure proper soft-start reset after fault condition. enable the enable (en) input allows the user to control the turning on or off the regulator for purposes such as power-up sequencing. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft-start-up begins. discharge mode (soft-stop) when a transition to shutdown mode occurs or the vin uvlo is set, the outputs discharge to gnd through an internal 100 switch. power mosfets the power mosfets are optimized for best efficiency. the on-resistance for the p-fet is typically 40m and the on-resistance for the n-fet is typically 30m . 100% duty cycle the isl8023, isl8024 features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the isl8023, isl8024 can no longer maintain the regulation at the output, the regulator completely turns on the p-fet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-fet. thermal shut-down the isl8023, isl8024 has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +125c, the isl8023, isl8024 resumes operation by stepping through the soft-start. applications information output inductor and capacitor selection to consider steady state and transient operations, isl8023, isl8024 typically uses a 1.0h output inductor. the higher or lower inductor value can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. it is recommended to set the ripple inductor current approximately 30% of the maximu m output current for optimized performance. the inductor ripple current can be expressed as shown in equation 3: the inductor?s saturation current rating needs to be at least larger than the peak current. the isl8023, isl8024 protects the typical peak current 6a. the satura tion current needs be over 7a for maximum output current application. isl8023, isl8024 uses internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended x5r or x7r minimum output capacitor values are shown in table 1. in table 1, the minimum output capacitor value is given for the different output voltage to make sure that the whole converter system is stable. additional output capacitance should be added for better performances in applic ations where high load transient or low output ripple is required. it is recommended to check the system level performance along with the simulation model. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to figure 2. the output voltage programming resistor, r 2 , will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor is typically between 10k and 100k , as shown in equation 4. if the output voltage desired is 0.6v, then r 3 is left unpopulated and r 2 is shorted. there is a leakage current from vin to phase. it is recommended to preload the output with 10a minimum. for better performance, add 15pf in parallel with r 2 (100k ). check loop analysis before use in application. vset marginally adjust vfb according to the ?electrical specifications? table on page 5. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. at least two 22f x5r or x7r ceramic capacitors are a good starting point for th e input capacitor selection. c ss f [] 3.33 t ss s [] ? = (eq. 2) i v o 1 v o v in -------- ? ?? ?? ?? ? lf s ? ------------------------------------ = (eq. 3) r 2 r 3 v o vfb ---------- 1 ? ?? ?? = (eq. 4)
isl8023, isl8024 16 fn7812.0 december 22, 2011 loop compensation design when there is an external resistor connected from fs to sgnd, comp pin is active for external loop compensation. the isl8023, isl8024 uses constant frequenc y peak current mode control architecture to achieve fast loop transient response. an accurate current sensing pilot device in parallel with the upper mosfet is used for peak current control si gnal and overcurre nt protection. the inductor is not considered as a state variable since its peak current is constant, and the system becomes single order system. it is much easier to design a type ii compensator to stabilize the loop than to implement voltage mode control. peak current mode control has inherent input voltage feed-forward function to achieve good line regulation. figure 39 shows the small signal model of the synchronous buck regulator. pwm comparator gain f m : the pwm comparator gain fm for peak current mode control is given by equation 5: where, s e is the slew rate of the slope compensation and s n is given by equation 6 where, r t is trans-resistance, which is the gain of the current amplifier. current sampling transfer function h e (s): in current loop, the current sign al is sampled every switching cycle. it has the following transfer function in equation 7: where, q n and n are given by power stage transfer functions transfer function f 1 (s) from control to output voltage is: where, transfer function f 2 (s) from control to inductor current is given by equation 9: where . current loop gain t i (s) is expressed as equation 10: the voltage loop gain with open current loop is equation 11: the voltage loop gain with cu rrent loop closed is given by equation 12: where, is the feedback voltage of the voltage error amplifier. if t i (s)>>1, then equation 12 can be simplified as equation 13: equation 13 shows that the system is a single order system, which has a single pole located at before the half switching frequency. therefore, a simple type ii compensator can be easily used to stabilize the system. d v in d i l in in i l + 1:d + l i co rc -av(s) d comp v r t fm he(s) + t i (s) k o v t v (s) i l p + 1:d + rc ro -av(s) r t fm he(s) t i (s) k o t(s) ^ ^ v ^ ^ ^ ^ ^ ^ figure 41. small signal model of synchronous buck regulator r lp gain (vloop (s(fi)) f m d ? v ? comp ---------------- 1 s e s n + () t s ----------------------------- - == (eq. 5) s n r t v in v o ? l p ------------------- - = (eq. 6) h e s () s 2 n 2 ------ - = s n q n -------------- 1 ++ (eq. 7) q n 2 --- ? = n f s = , f 1 s () v ? o d ? ----- - v in 1 s esr ----------- - + s 2 o 2 ------ - s o q p -------------- 1 ++ -------------------------------------- == (eq. 8) esr 1 r c c o ------------ - q p r o c o l p ----- - o 1 l p c o ---------------- - = , , = f 2 s () i ? o d ? ---- v in r o r lp + ---------------------- - 1 s z ------ + s 2 o 2 ------ - s o q p ------------- - 1 ++ -------------------------------------- == (eq. 9) z 1 r o c o ------------- = t i s () r t f m f 2 s () h e s () = (eq. 10) t v s () kf m f 1 s () a v s () = (eq. 11) l v s () t v s () 1t i s () + ---------------------- - = (eq. 12) k v fb v o --------- v fb , = l v s () v fb v o --------- r o r lp + r t ----------------------- 1 s esr ----------- - + 1 s p ------ - + --------------------- - a v s () h e s () --------------- p 1 r o c o ------------- , = (eq. 13) p
isl8023, isl8024 17 fn7812.0 december 22, 2011 figure 42 shows the type ii compensator and its transfer function is expressed as equation 14: where , compensator design goal: high dc gain loop bandwidth f c : gain margin: >10db phase margin: 40 the compensator design procedure is as follows: put compensator zero put one compensator pole at zero frequency to achieve high dc gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower. an optional zero can boost the phase margin. cz2 is a zero due to r 2 and c 3 . put compensator zero the loop gain t v (s) at cross over frequency of f c has unity gain. therefore, the compensator resistance r 1 is determined by equation 15. where, gm is the sum of the trans-conductance, g m , of the voltage error amplifier in each phase. compensator capacitor c6 is then given by equation 16. example: v in = 5v, v o = 1.8v, i o = 4a, fs = 1mhz, c o = 22f/3m , l = 1h, gm = 160s, r t = 0.20v/a, v fb =0.6v, s e = 440mv/s, s n =6.4 10 5 v/s, f c = 100khz, then compensator resistance r 6 = 100k . put the compensator zero at 1.5khz (~1.5x c o r o) , and put the compensator pole at esr zero which is 390khz. the compensator capacitors are: c 6 = 220pf, c 7 = 3pf (there is approximately 3pf parasitic capacitance from v comp to gnd; therefore, c7 optional). figure 43 shows the simulated voltage loop gain. it is shown that it has 90khz loop bandwidth with 70 phase margin and 10db gain margin. - + r6 v ref v fb vo gm v comp c7 - + c6 v ref v fb vo v comp figure 42. type ii compensator c3 r2 r3 a v s () v ? comp v ? fb ---------------- gm c 1 c 2 + ------------------- 1 s cz1 ------------ + ?? ?? 1 s cz2 ------------ + ?? ?? s1 s cp --------- - + ?? ?? -------------------------------------------------------- - = = (eq. 14) cz1 1 r 6 c 6 ------------- - cz2 1 r 2 c 3 ------------- - = cp , c 6 c 7 + r 1 c 6 c 7 --------------------- = , = 1 4 -- - to 1 10 ------ - ?? ?? f s cz1 1to3 () 1 r o c o ------------- = cz2 5to8 () 1 r o c o ------------- = r 6 2 f c v o c o r t gm v fb ? ------------------------------- - = (eq. 15) c 6 1 r 6 cz ---------------- - c 2 1 2 r 6 f esr ------------------------ - = , = (eq. 16) figure 43. simulated loop gain 60 45 30 15 0 -15 -30 100 1k 10k 100k 1m f (fi) 180 150 120 90 60 30 0 100 1k 10k 100k 1m f (fi) phase (vloop (s(fi))
isl8023, isl8024 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7812.0 december 22, 2011 for additional products, see www.intersil.com/product_tree pcb layout recommendation the pcb layout is a very important converter design step to make sure the designed converter works well. for isl8023, isl8024, the power loop is composed of the output inductor l?s, the output capacitor c out , the phase?s pins, and the pgnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them shou ld be direct, short and wide. the switching node of the conv erter, the phase pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed to vin pin as close as possible. and the ground of input and output capacitors should be connected as close as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl8023, isl8024 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 12/22/2011 fn7812.0 initial release.
isl8023, isl8024 19 fn7812.0 december 22, 2011 package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail ?x? jedec reference draw ing: mo-220 weed. 7.

▲Up To Search▲

Price & Availability of ISL8023AIRTAJZ

	To Download ISL8023AIRTAJZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .